Version Found: 1.7/1.8 with patch from (Xilinx Answer 53420)
Version Resolved: See (Xilinx Answer 45195)
When generating a MIG 7 series DDR3 design with the Debug Signals enabled, debug signals of interest are brought into ChipScope ILA and VIO cores, including signals specific to the OCLKDELAY stage of calibration. The OCLKDELAY calibration RTL was updated through the patch provided wtih (Xilinx Answer 53420). Due to the algorithm changes, the existing debug signals for this portion of calibration are out-of-date. This answer record details the outdated OCLKDELAY calibration debug signals.
The previous debug signals used to determine which edges were found and the associated taps were:
When looking at the results in the ChipScope tool after applying the patch in (Xilinx Answer 53420), only ocal_tap_cnt will have a value. All other signals will be zero. This is because ocal_edge1_found, ocal_edge2_found, ocal_edge1_taps, and ocal_edge2_taps are no longer used in the new algorithm.
Updates to the debug signals are under investigation and will be updated in a future release of MIG 7 series. In the meantime, the ocal_tap_cnt can be used to determine the ending tap placement after OCLKDELAY Calibration has completed.