Description

When running a timing simulation using the Vivado Simulator, the delays associated with the timing simulation netlist are not found. The waveform signals show no delay.

How do I associate the SDF based delays with the design, and when will this be repaired?

Solution

This is a known issue with the 2012.x Vivado toolset. The issue is repaired in the 2013.1 release of Vivado tools.

The issue arises when a VHDL based test structure is used to drive the Verilog based timing simulation netlist.

The work-around is to use the command line to run the Vivado Simulator and explicitly specify the SDF file and hierarchy using the -sdfmax switch.

          -sdfmax /<testbench_name>/uut=work.<sdf_filename>.sdf

For more information on the command line operation of the Vivado Simulator, please see the Vivado Simulator User's Guide.