We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54930

When running a mixed-language timing simulation with the Vivado Simiulator, the associated SDF delays are not found


When running a timing simulation using the Vivado Simulator, the delays associated with the timing simulation netlist are not found. The waveform signals show no delay.

How do I associate the SDF based delays with the design, and when will this be repaired?


This is a known issue with the 2012.x Vivado toolset. The issue is repaired in the 2013.1 release of Vivado tools.

The issue arises when a VHDL based test structure is used to drive the Verilog based timing simulation netlist.

The work-around is to use the command line to run the Vivado Simulator and explicitly specify the SDF file and hierarchy using the -sdfmax switch.

          -sdfmax /<testbench_name>/uut=work.<sdf_filename>.sdf

For more information on the command line operation of the Vivado Simulator, please see the Vivado Simulator User's Guide.

AR# 54930
Date 03/27/2013
Status Active
Type General Article
Page Bookmarked