AR# 54958

Description

synth_design is a Tcl command used to run synthesis on a HDL design using Vivado Synthesis.

This Tcl command is used both in project flow mode via the TCL console, and in non-project flow mode.

In project flow mode, launch_runs synth_1 and this internally calls the command synth_design.

The Tcl command set_property can be used to set any synthesis properties.

This answer record describes the various optional synth_design synthesis switch options.

Solution

Description of Switches:

-name <design_name>: [Optional]

This switch is used to open the design after synthesis completion.

Example syntax: synth_design -name synth_1 (Synthesized design with name is opened after synthesis)

-part <xilinx_device>: [Optional]

This switch is used to specify the targeted Xilinx device for the design to be synthesized. If the part is not specified, the default part assigned to the project (used while creating a project) will be used.

Example syntax: synth_design -part xc7k70tfbg676-2 (Kintex-7 Xilinx device is targeted for synthesis)

-constrset <constraints_fileset>: [Optional]

It is used for specifying a particular set of xdc constraint files used in synthesis. It is helpful when multiple constraint filesets or constraint files are present. Vivado does not support UCF. This command refers to the already created or existing fileset.

Use create_fileset to create a fileset.

Example syntax: synth_design -part xc7k70tfbg676-2 -constrset constr_1 (Constraint fileset targeted was constr_1)

-top <top_module>: [Optional]

It is used to specify the top module name.

Syntax: synth_design -part xc7k70tfbg676-2 -top module1

Note: If you use the find_top command to define the -top option, make sure you provide only one top if it returns multiple prospects.

-include_dirs <search_directories>: [Optional]

This is used for only Verilog designs. It is used for specifying the directories to search for Verilog `include files.

Syntax: synth_design -part xc7k70tfbg676-2 -top module1 -include_dirs /path/to/directories/

-generic <name> = <value>: [Optional]

This switch is used to specify a VHDL generic value or Verilog parameter value. Here the name indicates the name of the parameter or generic and value indicates the value to be assigned. 

If there are two or more generic values to be assigned, use the generic multiple times. Syntax below:

Syntax: synth_design -part xc7k70tfbg676-2 -generic depth=512 -generic width=64

Note: Do not use spaces between the name, = (equal to), value.

Note: When specifying binary values for boolean or std_logic VHDL generic types, you must specify the value using the Verilog bit format, rather than standard VHDL format:

0 = 1`b0

01010000 = 8`b01010000

-verilog_define name=<text>: [Optional]

Used to provide values for the `define and `ifdef statements. To specify two or more statements, use the verilog_define multiple times.

Syntax: synth_design -verilog_define name=value -verilog_define name=value

Note: Do not use spaces between the name, = (equal to), value

-flatten_hierarchy <rebuilt/full/none>: [Optional]

As the name indicates, -flatten_hierarchy determines how synthesis controls hierarchy. The valid values:

•  
  • rebuilt (default value): This will rebuild the original hierarchy of the RTL design after synthesis has completed.
  • full: Flatten the hierarchy of the design.
  • none: This value do not flatten the hierarchy of the design. This will preserve the hierarchy of the design and also limits the design optimization being done by the tool.

Syntax: synth_design -part xc7k70tfbg676-2 -flatten_hierarchy rebuilt

-gated_clock_conversion <off/on/auto>: [Optional]

This switch converts the gated logic to utilize the flop enable pins when available. By default, the value is OFF. 

This will utilize available flop enables to convert gating logic in the design. This optimization can eliminate logic and simplify the netlist. 

This can also be performed on the synthesized netlist using opt_deisgn command. 

This option additionally requires gated_clk attribute to be specified in the HDL. Valid values are off, on, auto.

•  
  • OFF - Disables the conversion of clock gating logic during synthesis, regardless of the use of the GATED_CLOCK property in the RTL design.
  • ON - Converts clock gating logic based on the use of the GATED_CLOCK property in the RTL design.
  • AUTO - Performs gated clock conversion when the tool detects a gate with a valid clock constraint irrespective of the GATED_CLOCK attribute in the RTL.

Syntax: synth_design -part xc7k70tfbg676-2 -gated_clock_conversion off

-directive<Default/RuntimeOptimized/AreaOptimizedLow/AreaOptimizedHigh>: [Optional]

A Synthesis directive. It makes the synthesis tool to achieve specific design objectives. Values are case-sensitive. Valid values are as follows:

•  
  • Default: Normal synthesis run
  • RuntimeOptimized: This indicates that fewer timing optimizations will be performed, and some RTL optimizations will not be performed.
  • AreaOptimizedLow:
  • AreaOptimizedHigh:

-resource_sharing<auto/on/off>: [Optional]

This switch makes the synthesis tool to share arithmetic operators like adders or subtractors between different signals, rather than creating new operators.

This can result in better area utilization when it is turned on. By default, the value is auto.

-control_set_opt_threshold <greater than or equal to 1>:

This switch is used to specify threshold for synchronous control set optimization to lower number of control sets. 

The number set to this value specifies how large the fanout of a control set should be before it starts using it as a control set.

For example, if control_set_opt_threshold is set to 10, a synchronous reset that only fans out to 5 registers would be moved to the D inputs logic, rather than using the reset line of a register. 

However, if it is set to 4, then the reset line is used. Default: 4

-rtl : [Optional]

Performs the elaboration of the design and opens it.

Syntax: synth_design -part xc7k70tfbg676-2 -rtl

-bufg <value>: [Optional]

Used to specify the maximum number of BUFGs (global clock buffers) to be used during synthesis. This includes instantiated BUFGs in the RTL. 

The value should be >= 1. The default value is 12.

Syntax: synth_design -part xc7k70tfbg676-2 -bufg 3

-fanout_limit <value>: [Optional]

This switch limits the maximum net fanout applied during synthesis run. 

The value should be >=1. Default value is 10,000.

This switch does not affect control signals (such as set, reset, clock enable). Instead use the MAX_FANOUT attribute in RTL to replicate these signals if needed.

Syntax: synth_design -part xc7k70tfbg676-2 -fanout_limit 2000

-mode <default/out_of_context>: [Optional]

This specifies the mode of the synthesis to be run on the design.

• Default: This option is used for normal synthesis.
• Out_of_context: This option is used to specify that the module is being used in hierarchy design. This mode turns off I/O buffer insertion for the module and marks it as OOC, to facilitate its use in the HD flow.

Note: There is no need to specify no_iobuf with this mode (i.e., out_of_context). out_of_context mode is recommended instead of -no_iobuf.

Syntax: synth_design part xc7k70tfbg676-2 -mode out_of_context

-fsm_extraction <off/one_hot/sequential/johnson/gray/auto>: [Optional]

This option is used to identify the state machine and the type of encoding applied while running synthesis. The default value is OFF. The valid values:

•  
  • one_hot: Its principle is to associate one code bit and also one flip-flop to each state. At a given clock cycle during operation, one and only one bit of the state variable is asserted. Only two bits toggle during a transition between two states. One-Hot State Encoding is appropriate with most FPGA targets where a large number of flip-flops are available. It is also a good alternative when trying to optimize speed or to reduce power dissipation.
  • sequential: Sequential State Encoding consists of identifying long paths and applying successive radix two codes to the states on these paths. Next, state equations are minimized.
  • gray: Gray State Encoding guarantees that only one bit switches between two consecutive states. It is appropriate for controllers exhibiting long paths without branching. In addition, this coding technique minimizes hazards and glitches. Very good results can be obtained when implementing the state register with T flip-flops.
  • johnson: Like Gray State Encoding, Johnson State Encoding shows benefits with state machines containing long paths with no branching.
  • auto: The tool tries to select the best suited encoding algorithm for each FSM in the design. It may use different encoding styles for different FSMs in the same design.

Note: Use -fsm_extraction off to disable finite state machine extraction in Vivado Synthesis. This will override the FSM_ENCODING property if specified in RTL.

-no_lc: [Optional]

LUT combining basically merges LUT pairs with common inputs into single dual-output LUT6s in order to improve design area. User can disable it by using -no_lc.

Syntax: synth_design -part xc7k70tfbg676-2 -no_lc

-shreg_min_size <integer>: [Optional]

Used to specify the minimum length for a chain of registers to be mapped onto SRL. The default value is 3

Syntax: synth_design -part xc7k70tfbg676-2 -shreg_min_size 4

-max_bram <arg>: [Optional]

Used to specify the maximum number of block RAM to infer during synthesis. The specified value will not exceed the available block RAM limit of the target device. Default Value: -1.

Note: A value of 0 directs Vivado synthesis to not infer BRAMs in the design, but is not a recommended value.

-max_dsp <arg>:[Optional]

Used to specify the maximum number of DSPs to infer during synthesis. The specified value will not exceed the available DSP limit of the target device. Default Value: -1.

Note: A value of 0 directs Vivado synthesis to not infer DSPs in the design, but is not a recommended value.

-quiet: [Optional]

This switch executes the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution. i.e., Only errors occurring inside the command will be trapped.

-keep_equivalent_registers: [Optional]

Works like the synthesis KEEP attribute to prevent the merging of registers during optimization.

-verbose: [Optional]

This returns all messages (i.e., every message) during synthesis. This will override any message limits if present.

-rtl_skip_ip - [Optional]

When elaborating the RTL design with the -rtl option, this option causes the Vivado Design Suite to skip loading the DCP files for out-of-context modules in the design, and instead load a stub file to treat the OOC modules as a black boxes. This can significantly speed elaboration of the design.

-rtl_skip_constraints - [Optional]

When elaborating the RTL design with the -rtl option, this option causes the Vivado Design Suite to skip loading any design constraints (XDC) into the elaborated design

-cascade_dsp [ auto | tree | force ] - [Optional]

Specifies how to implement adders that add DSP block outputs. Valid values include auto, tree, force. The default setting is auto.

[Optional] -- indicates optional switches.

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