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AR# 55001

SelectIO Wizard v5.0 - Verilog instantiation changed from uppercase to lowercase


In the Vivado 2013.1 tools, if you upgrade a previous version of the SelectIO Wizard IP with a Verilog instantiation, error messages similar to the following appear:

"[Synth 8-285] failed synthesizing module 'selectio_wiz_v4_2_0_selectio_wiz' ["/testing.srcs/sources_1/ip/selectio_wiz_v4_2_0/selectio_wiz_v4_2_0_selectio_wiz.v":55]"


To drive consistency between Xilinx IPs, signal names in the Verilog version of the cores have been changed to use all lowercase, therefore, the signal names in the IP instantiation are now in lowercase.

For example, the DATA_IN_FROM_PINS signal is now data_in_from_pins in v5.0.

After the upgrade is completed, the instantiation in the custom design will need to be replaced with signal names in lowercase.

AR# 55001
Date 03/28/2013
Status Active
Type General Article
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