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AR# 55005

LogiCORE IP Aurora 64B66B v8.0 - Verilog instantiation changed from uppercase to lowercase


In the Vivado 2013.1 tools, if you upgrade from a previous version of the Aurora 64B66B IP with a Verilog instantiation, the tools will issue an error message for each port. For example:

"ERROR: [Synth 8-448] named port connection 'S_AXI_TX_TDATA' does not exist for instance 'aurora_64b66b_v7_3_0_block_i' of module 'aurora_64b66b_v7_3_0' [/project_2/example_project/


To drive consistency between Xilinx IPs, signal names in Verilog versions of the cores have been changed to use all lowercase.

Therefore, the signal names in the IP instantiation are now in lowercase. For example, the "S_AXI_TX_TDATA" signal is now "s_axi_tx_tdata" in v9.0.

After the upgrade is completed, the instantiation in the design will need to be replaced with signal names in lowercase.

Aurora 64B66B v8.0 require the following additional updates.

  1. Update MMCM_LOCKED port to gt_pll_lock
  2. Update BUFG instance name "rxrecclk_mmcm_bufg_i" in the following timing constraint to "rxrecclk_bufg_i".
      create_clock -name TS_rxrecclk_32 -period 10.24     [get_pins -hier *rxrecclk_mmcm_bufg_i/O]

Revision History
05/31/2013 - Initial release

AR# 55005
Date 06/03/2013
Status Active
Type General Article
  • Aurora 64B/66B
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