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AR# 55012

MIG 7 Series - The .vho instantiation template is not generated when project option is set to VHDL; only .veo (Verilog instantiation template) is generated

Description

Version Found: MIG 7 Series v1.9
Version Resolved: See (Xilinx Answer 45195)

When the CORE Generator project options are set to VHDL, a .vho instantiation template is not generated. Only a .veo (Verilog instantiation) template is instantiated.

Solution

The Verilog version must be used as a work-around, or the HDL rtl code can be brought into the design.
AR# 55012
Date Created 03/20/2013
Last Updated 12/02/2013
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series