We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55012

MIG 7 Series - The .vho instantiation template is not generated when project option is set to VHDL; only .veo (Verilog instantiation template) is generated


Version Found: MIG 7 Series v1.9
Version Resolved: See (Xilinx Answer 45195)

When the CORE Generator project options are set to VHDL, a .vho instantiation template is not generated. Only a .veo (Verilog instantiation) template is instantiated.


The Verilog version must be used as a work-around, or the HDL rtl code can be brought into the design.
AR# 55012
Date 12/02/2013
Status Active
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • MIG 7 Series
Page Bookmarked