AR# 55018

Zynq-7000 SoC, APU - A spurious event 0x63, “STREX passed,” might be reported on an LDREX instruction


A write to Strongly Ordered memory region, followed by the execution of an LDREX instruction, might cause the STREX passed event (0x63) to be signaled even if no STREX instruction is executed.

As a result of the write, the reported count of 0x63 events might be more than the actual number that took place. This issue also affects the associated PMUEVENT[27] signal which again will report the same spurious events.


The following conditions have to be met in order for the problem to occur:

  • The processor executes a write instruction to a Strongly Ordered memory region.
  • The processor executes an LDREX instruction.
  • No DSB instruction is executed, and there is no exception call or exception return between the write and the STREX instructions

Under these conditions, if the write instruction to Strongly Ordered memory region receives its Acknowledge (BRESP response on AXI) while the LDREX is being executed, the stated malfunction can occur.

Impact:Trivial. Occurrence of this problem leads to a faulty count of event 0x63, or incorrect signaling of PMUEVENT[27].
Work-around:Insert a DMB or DSB instruction between the write to Strongly Ordered memory region and the LDREX instruction.
Configurations Affected:Systems that use the CPUs.
Device Revision(s) Affected:All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences.

Revision History
05/16/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 SoC Devices - Silicon Revision Differences N/A N/A
AR# 55018
Date 06/13/2018
Status Active
Type Design Advisory