A write to Strongly Ordered memory region, followed by the execution of an LDREX instruction, might cause the STREX passed event (0x63) to be signaled even if no STREX instruction is executed.
As a result of the write, the reported count of 0x63 events might be more than the actual number that took place. This issue also affects the associated PMUEVENT signal which again will report the same spurious events.
The following conditions have to be met in order for the problem to occur:
Under these conditions, if the write instruction to Strongly Ordered memory region receives its Acknowledge (BRESP response on AXI) while the LDREX is being executed, the stated malfunction can occur.
|Impact:||Trivial. Occurrence of this problem leads to a faulty count of event 0x63, or incorrect signaling of PMUEVENT.|
|Work-around:||Insert a DMB or DSB instruction between the write to Strongly Ordered memory region and the LDREX instruction.|
|Configurations Affected:||Systems that use the CPUs.|
|Device Revision(s) Affected:||All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences.|
05/16/2013 - Initial release