We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55037

Design Advisory for Spartan-3A and Spartan-6 - After SelectMAP configuration, when Readback CRC is enabled and an ABORT is triggered, spurious failures might be flagged in Readback CRC


The Readback CRC feature on Spartan-6 and Spartan-3A devices can flag errors if there is activity on the CS and RDWR pin of the SelectMap interface after Configuration has completed as FPGA Configuration might be corrupted. There can also be functional failures in the design after this because of FPGA configuration corruption.  This can occur with or without the "Bitgen -g Persist" option set to keep the SelectMap interface active. It was previously documented that the CS and RDWR pins would be ignored unless "Bitgen -g Persist:Yes" is set. The failure occurs after SelectMAP configuration when the Readback CRC feature is running and an ABORT sequence is triggered. For details and Timing Diagrams of how an ABORT is triggered, see the "SelectMAP ABORT" section of the Spartan-6 Configuration User Guide (UG380).

All of the following conditions must be met in order to have exposure to the issue:

  • In SelectMAP configuration mode
  • POST_CRC running
  • RDWR_B and CSI_B reused as input/bidir after configuration and toggled to trigger ABORT
  • ICAP is not instantiated in the FPGA design


There are a number of work-arounds that can be applied.

Work-around 1

Instantiate the ICAP primitive in the design. This prevents RDWR_B/CSI_B signal monitoring. When instantiating the ICAP, a free runnning clock should be supplied to the CLK pin. This clock will be the clock source for the Readback CRC feature and is required. For information on how to instantiate the ICAP primitive, refer to the "Spartan-6 Libraries Guide for HDL Designs".

Following is an example of an ICAP instantiation. In these instances, CE and RDWR are pulled High disabling the ICAP, and a clock is provided. All other ports are left open.


Example ICAP instantiation

// ICAP_SPARTAN3A: Internal Configuration Access Port

ICAP_SPARTAN3A test_icap (

.BUSY(), // Busy output

.O (), // 8-bit data output

.CE(1'b1), // Clock enable input

.CLK(clk), // Clock input for the POST_CRC logic

.I(8'h00), // 8-bit data input

.WRITE(1'b1) // Write input


// End of ICAP_SPARTAN3A_inst instantiation



   .BUSY(), // Busy output

.O (), // 8-bit data output
.CE(1'b1), // Clock enable input
.CLK(clk), // Clock input for the POST_CRC logic
.I(8'h00), // 8-bit data input
.WRITE(1'b1) // Write input

Work-around 2
Do not reuse the RDWR_B and CSI_B after SelectMAP configuration. This issue can be avoided by ensuring that CS and RDWR do not toggle once Configuration has completed.

Work-around 3
Control the RDWR_B and CSI_B signal activity so that an ABORT sequence is not triggered. Depending on the pin usage, it might be possible to avoid the ABORT as described in the the "SelectMAP ABORT" section Spartan-6 Configuration User Guide (UG380)

Work-around 4
Use a different configuration mode other than SelectMAP mode (i.e., Serial mode).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A
55115 Design Advisory Master Answer Record for Spartan-3A/3AN/3A DSP FPGAs N/A N/A
AR# 55037
Date 03/28/2013
Status Active
Type Design Advisory
  • Spartan-3AN
  • Spartan-3A DSP
  • Spartan-3A
  • Spartan-6