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In the 10-Gigabit Ethernet MAC v12.0 Internal XGMII interface VHDL example design, the tx_dcm_locked input to the physical interface block is not driven.
This results in the example design simulation not completing.
To work around this issue, change the tx_dcm_locked input for ten_gig_eth_mac_0_physical_if in the core_name_example_design.vhd file.
from
tx_dcm_locked => tx_dcm_locked_reg,
to
tx_dcm_locked => tx_dcm_locked,
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
54252 | LogiCORE IP 10G Ethernet MAC - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions | N/A | N/A |
AR# 55038 | |
---|---|
Date | 09/22/2014 |
Status | Active |
Type | Known Issues |
IP |
|