Installation instructions and a list of the Release Notes and Known Issues in System Generator for DSP 14.4 tools are included in this answer record. A successful installation of ISE Design Suite 14.4 changes your design tools version number to 14.4 (verify by running xlVersion, or typing 'ver' at the MATLAB prompt).
Release Notes and New Features in System Generator for DSP 14.4
Which versions of System Generator for DSP and AccelDSP synthesis tool are compatible with which versions of ISE software and MATLAB? See (Xilinx Answer 17966)
Frequently Asked Questions
Installation and Setup(Xilinx Answer 17966)
- Which versions of System Generator for DSP and the AccelDSP synthesis tool are compatible with which versions of ISE tools and MATLAB? Please note theAccelDSP synthesis tool is not supported in tools later than 11.4.(Xilinx Answer 32257)
- How can I tell if the DSP tools are installed and configured for use in MATLAB? (Xilinx Answer 24842)
- How can I switch between multiple versions of System Generator for one MATLAB installation?
MATLAB and SimuLink Interaction (Xilinx Answer 31933)
- Why do I receive an error message stating "continuous sample times are not allowed" when driving a Simulink Spectrum Scope with Xilinx System Generator blocks? (Xilinx Answer 21750)
- Why do I receive a "xlSimulationRequired" or "Reference to a cleared variable sysgen_return_status" error when I try to generate the design? (Xilinx Answer 23000)
- An indeterminate input data (also known as a NAN) error occurs when design is simulated. (Xilinx Answer 24616)
- Why am I unable to access the quantization parameters in the FDATool in System Generator? (Xilinx Answer 25255)
- Why do I receive a Simulink message stating, "Use of this data type requires a fixed-point license, but license checkout failed"? (Xilinx Answer 23328)
- What is the recommended Simulink simulation solver? Why do I see incorrect behavior when a fixed-step solver is used? (Xilinx Answer 32810)
- Why does my data not appear downsampled when I use "first value of frame" with a latency of 0 with the downsample block? (Xilinx Answer 32856)
- Why do I receive an internal error or see MATLAB crash if I use the Simulink Simulation option "Accelerator"?
General (Xilinx Answer 24257)
- Why do I see an instantiated register called "xlpersistentdff" in a System Generator for DSP design? (Xilinx Answer 19599)
- JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. (Xilinx Answer 29430)
- Why do I receive a standard exception error message when I generate my model? (Xilinx Answer 35474)
- How can I simulate my Multiple clock domain System Generator design in VHDL?(Xilinx Answer 37984)
- I have a corrupted MDL design file. How do I clear the cache for System Generator?(Xilinx Answer 44617)
- When creating a netlist I get a message "An internal error occurred in the Xilinx Blockset Library." Why? (Xilinx Answer 44146)
- 13.2 System Generator for DSP - I do not get any output from Viterbi v7.0 in Simulink Simulation? Why?(Xilinx Answer 46069)
- Why am I receiving an exception message with the FIR Compiler v6.3?(Xilinx Answer 44874)
- Why does the convert block not handle quantization and overflow in floating point? (Xilinx Answer 41563)
- "ERROR: A license checkout has failed for System Generator for DSP" Why did this occur?
(Xilinx Answer 50973)
- System generator for DSP v13.x, 14.1 and 14.2 - Produces an Internal Error message with a valid license file
Known Issues(Xilinx Answer 47863)
- Where can I find the PlanAhead tutorial files mentioned in the release notes and UG640?(Xilinx Answer 43515)
- System Generator for DSP v13.x - Can I configure the ML605 board via the ethernet interface? (Xilinx Answer 43570)
- System Generator for DSP - If I use the user-defined output from a basic block e.g AddSub, Mult, CMult, my performance seems to be reduced. Why?(Xilinx Answer 45838)
- Should I initialize Mcode Outputs? (Xilinx Answer 45839)
- Are there any optimization options to minimize area or maximize speed for the Mcode Block?(Xilinx Answer 44151)
- What is the flow for bringing a design with a tri-state port through System Generator (black box) and finally into EDK?(Xilinx Answer 45516)
- System Generator GUI reports incorrect latency value of Divider Generator (AXI) v4.0. Is there a work-around? (Xilinx Answer 36329)
- Username containing special characters (i.e umlauts) could cause Sysgen Errors. How can I work around this?