AR# 55083


AXI Bridge for PCI Express v1.07a - Root Port cannot Enumerate (Send Configuration Packets) to Devices with Non-Zero Device Number


Version Found: v1.07a
Version Resolved and other Known Issues: See (Xilinx Answer 44969).

Root Port cannot enumerate (send configuration packets) to devices with non-zero device number.


This is currently a limitation in the core and is also documented in the Product Guide for this core.

To work around the issue, use the attached patch (axi_pcie_v1_07_a_axi_enhanced_cfg_slave.v file) for AXI Bridge for PCIe core v1.07a only. The patch has not been tested with older AXI Bridge for PCIe core versions.

To apply the patch:

  1. Upgrade the AXI Bridge for PCIe core to v1.07.a released in ISE 14.5 tool.
  2. Make the AXI Bridge for PCIe core local by right-clicking the core, then choose Make this IP local within XPS tool.
  3. Navigate to the project_directory/pcores/axi_pcie_v1_07_a/hdl/verilog and replace the core_name_a_axi_enhanced_cfg_slave.v file with the attached file in this answer record.
  4. Within XPS tool, select Project -> Clean All Generated Files to remove any implemented design.
  5. Re-run Synthesis and Implementation.

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

05/15/2013 - Initial release


Associated Attachments

Name File Size File Type
axi_pcie_v1_07_a_axi_enhanced_cfg_slave.v 120 KB V

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 55083
Date 08/26/2013
Status Active
Type Known Issues
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