This answer record contains a list of Vivado Design Suite user interface and project management known issues for Vivado IDE 2013.x.
Outstanding Known Issues in Vivado Design Suite 2013.4
(Xilinx Answer 51689) - Starting Vivado on a processor that does not support sse2, fails with rdiArgs.sh: line 95: 3012 Illegal instruction "$RDI_PROG" "$@"
(Xilinx Answer 53011) - There is a delay in the output to the "Log" tab in the "Properties" window in comparison with the main "Log" pane
(Xilinx Answer 53243) - "Replace File" directory browser does not update "Date Modified" field
(Xilinx Answer 55052) - Vivado does not preserve XDC wildcards in generated Design Check Point (DCP)
(Xilinx Answer 55418) - Message suppression rules are not editable
(Xilinx Answer 55444) - Data2mem fails if the path to the BMM file contains a directory named "microblaze"
(Xilinx Answer 57293) - The report_environment command takes a long time when "Fetching license information..." for floating licenses
(Xilinx Answer 58504) - 2013.4 Vivado - JAVA Runtime Environment (JRE) is not picked up using MYVIVADO environment variable
Known Issues Resolved in Vivado 2013.4(Xilinx Answer 57299) - 2013.3 Vivado - The set_external_delay command incorrectly propagates to the routed DCP for an mmcm IP synthesized out of context (OOC)
Known Issues Resolved in Vivado 2013.3
(Xilinx Answer 54283) - Vivado interprets EDIF netlist keywords as case sensitive
(Xilinx Answer 54317) - Non-project IP core "does not match the current project part"
(Xilinx Answer 55414) - report_environment does not provide all the information expected (comparable to XINFO)
(Xilinx Answer 55470) - A Vivado project containing an IP Integrator (IPI) design block (.db file) loses implementation status when the design is closed and reopened
(Xilinx Answer 56386) - JAVA out of memory error incorrectly lists '49797MB' available
(Xilinx Answer 56492) - Behavioral simulation fails (<core_name> not found) for designs with IP cores with a Design Check Point (DCP) generated in Vivado IDE
(Xilinx Answer 56549) - The +incdir+ option is not written in .do files created from Vivado for System Verilog files
(Xilinx Answer 56565) - ISEWarp.sh and ISEWrap.js created in the synthesis run directory do not follow umask settings
(Xilinx Answer 56626) - A critical warning occurs "[Constraints 18-639]" that suggests I have set an IOB property to FALSE even though it is set to TRUE
(Xilinx Answer 56750) - A redundant line is added in the entity declaration when creating VHDL source in Add sources --> Create file
(Xilinx Answer 56814) - Vivado closes unexpectedly when trying to reconnect to a server in a hardware session
(Xilinx Answer 56845) - The Zynq ZC702 board was incorrectly listed as Version 3.0 in Vivado 2013.2
(Xilinx Answer 56887) - reimport_files command does not work properly in Tcl mode wihout -force option
(Xilinx Answer 57010) - The Virtex VC707 board was incorrectly listed as Version 2.0 in Vivado 2013.2
(Xilinx Answer 57136) - "Save as PDF" does not work in Vivado 2013.2 for saving schematic to non-default location
(Xilinx Answer 57242) - Synthesizing a design with many instances of the same DCP processes the DCP for each instance (extends run time)
(Xilinx Answer 57244) - "Migrate to RTL" gives: ERROR: [Common 17-70] Application Exception: ProjUtils::setConstrsTypeOrError: Illegal CONSTRS_TYPE: 'CT_UNKNOWN'
(Xilinx Answer 57299) - The set_external_delay command is incorrectly propagated to the routed DCP for an mmcm IP synthesized out of context (OOC)
(Xilinx Answer 57525) - The help of add_cells_to_pblock contains the incorrect example
(Xilinx Answer 57649) - Saving Tcl command line constraints may change the constraint compile order
(Xilinx Answer 57717) - Asian language characters in Vivado Text Editor might appear corrupted when a file is closed and reopened
(Xilinx Answer 57977) - Archiving and unpacking a synthesized design shows the synthesis run becomes out of date
(Xilinx Answer 58047) - The Tcl set_property -help incorrectly indicates that the value will be returned when successful
(Xilinx Answer 58304) - In Vivado 2013.2 and older tool versions, multiple synthesis and implementation runs cannot be launched together
Known Issues Resolved in Vivado 2013.2
(Xilinx Answer 53778) - "Go To Instantiation" option for Design view leads to incorrect instantiation location
(Xilinx Answer 54992) - CTRL-U (unplace) and CTRL-W (swap) shortcuts require context menu to be opened before being active
(Xilinx Answer 55412) - Drag and drop placement of SERDES or DDR Cells to BELs in Device Editor does not work
(Xilinx Answer 55416) - Invalid message "WARNING: [Project 1-153] The current project part 'xc7vx485tffg1157-1' does not match with the 'XILINX.COM:ZYNQ:ZC702:C' board part settings."
(Xilinx Answer 55438) - Vivado WebPACK install results in "ERROR: [board-21-45]" when I create a new project
(Xilinx Answer 55904) - The percentage of memory in the utilization report is understated
(Xilinx Answer 54992) - CTRL+U shortcut to unplace elements does not work in Vivado or PlanAhead tools
(Xilinx Answer 55506) - Sourcing a Tcl file created with write_project_tcl results in "ERROR: [Common 17-69] Command failed: Invalid constraints filename specified"
(Xilinx Answer 55507) - write_project_tcl error leads to: "ERROR: [Vivado 12-563] The file type 'TCL' is not user settable."
(Xilinx Answer 56419) - Vivado exists without an error message on Linux platform if the DISPLAY variable is set incorrectly
(Xilinx Answer 56420) - Message suppression causes ERROR: [Common 17-165] when project path contains white space
(Xilinx Answer 57650) - Modifying USED_IN from the IP Property Editor causes error: "Command failed: exec command in TCL console for details"
(Xilinx Answer 57867) - The Vivado IDE appears to hang when opening the Timing Constraints view