I tried to perform the quick test to implement both CAN (Controller Area Network) using the EMIO (by pass the Transceiver). In the PL, I tied the CAN0_Rx to CAN1_Tx, and CAN0_TX to CAN1_RX. If I ran the loopback test, both CAN work fine. However, when I enable the NORMAL mode, the CAN receiver does not receive any CAN message.
Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000. A tip can be a snippet of code, a snapshot, a diagram, or a full design implemented with a specific version of the Xilinx tools. It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs. Limited support is provided by Xilinx on these Example Designs.
|Design Type||PS and PL|
|Xilinx Tools Version||EDK 14.4|
Note: A version of the design built using Vivado IP Integrator is also attached.
Simply, create a new Vivado project targeting the ZC702.
Source the .tcl to create the block design.
Add the constraints files.
Generate the output products.
Create the HDL wrapper and generate the bitstream.
You cannot simply connect TX to RX. CAN is a single wire protocol, so that means TX and RX need to be on the same line shorted.
Therefore, you need to AND the CAN0.TX and CAN1.TX, and then connect the signal to CAN0.RX and CAN1.RX.
(CAN0_TX and CAN1_TX) connected to CAN0_RX
(CAN0_TX and CAN1_TX) connected to CAN1_RX
The example provided by Xilinx uses the "LOOPBACK" mode to self check a single controller. You can easily modify the example and use it for this test case.
Here are a few hints:
Define two DEVICE_ID and two driver instances:
Initialize both controller in NORMAL mode (instead of LOOPBACK mode):
Send with one controller and receive with the other:
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