AR# 55134


MIG 7 Series - All interfaces have pll_locked and not mmcm_locked tied to their reset structure


Version Found: v1.5
Version Resolved: See (Xilinx Answer 45195) and (Xilinx Answer 54025)

All MIG 7 Series interfaces use a Phase Locked Loop (PLL) with its LOCKED signals tied into the reset structure.

An additional MMCM was added starting with the MIG 7 series v1.5 (See (Xilinx Answer 47043)), but the LOCKED signal was not tied into the reset structure.


This is not expected to cause failures within the MIG designs but can be corrected by making the following changes within infrastructure.v:


assign rst_tmp_phaser_ref = sys_rst_act_hi | ~pll_locked_i | ~iodelay_ctrl_rdy;


assign rst_tmp_phaser_ref = sys_rst_act_hi | ~mmcm_locked | ~iodelay_ctrl_rdy;

Revision History
04/03/2013 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 55134
Date 08/18/2014
Status Active
Type Known Issues
People Also Viewed