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AR# 55135

Vivado Synthesis - Unsupported SystemVerilog Constructs


This answer record lists the SystemVerilog constructs and features that are not supported by Vivado Synthesis.


Vivado Synthesis does not support the following SystemVerilog supported constructs and features:

  • Alias
  • Arrays of Interfaces
  • Dynamic Arrays
  • Assert Statements
  • Class
  • Virtual Ports
  • Virtual Functions
  • Unpacked Unions
  • Tagged Unions in Loops
  • Hierarchical reference to any interface with a given modport name - For example: interface_name.modport_name reference_name


AR# 55135
Date 10/08/2014
Status Active
Type Known Issues
  • Vivado Design Suite
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