UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55138

MIG 7 Series RLDRAM II - incorrect error message for data mask pin allocation when verifying pin out in MIG GUI

Description

Version Found: v1.9
Version Resolved: See (Xilinx Answer 45195) and (Xilinx Answer 54025)
 
When verifying a custom pinout using the Fixed Pin Out mode or "Verify Pin Changes and Update Design" mode, the following error message is displayed:

ERROR : The port "rldii_dm[1]" is not aligned with its strobe pair  "rldii_qk_p[1]" and "rldii_qk_n[1]"Mask  component ports should be allocated either in the same bank or above or below bank.

 

 

 

Solution

This is a false error message as Data Mask (DM) does not have an alignment requirement with QK/QK#.

However, this does indicate a pin out violation with DM elsewhere. 

To work around the DM violation make sure that all of the DM pin out requirements are being met:

Data Mask (DM) must be placed with one of the corresponding data byte lanes it is associated with.

For the x18 device, DM[0] corresponds to DQ[8:0] and DM[1] to DQ[17:9], while for the x36 device, DM[0] corresponds to DQ[8:0]/DQ[26:18] and DM[1] to DQ[17:9]/DQ[35/27].
 
Revision History
04/03/2013 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 55138
Date 03/20/2017
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series
Page Bookmarked