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AR# 55147

Artix-7 - GTP - example design v2.5 - not working when ChipScope is disabled, rxresetdone never goes high

Description

The example design for Artix-7 GTP v2.5 is not starting properly when ChipScope is disabled.

rxresetdone never goes high.

Solution

This is an issue with the behavior of the startup FSMs in the example design, especially the gtrxreset_t signal, and will be fixed in a future version.

The GTP will start normally  when generating the TX and RX reset and the userrdy signals according to user guide (UG482).

 

This can be shown on an AC701 board. 

The GTP always comes out of reset after using the push buttons to which the resets were connected (with the PLL lock signal high) and the userrdy signals are created from a counter running on the USRCLK.

The minimum change necessary here is to bring in the RX reset signal differently and disconnect the gtrxreset_t signal from the RX reset FSM in the *_init module.

It is also necessary to adapt the STABLE_CLOCK_PERIOD parameter value to the used frequency of the system clock in this module, as this is currently not changed from the wizard.

 

AR# 55147
Date Created 03/26/2013
Last Updated 03/18/2015
Status Active
Type General Article
Devices
  • Artix-7
IP
  • 7 Series FPGAs Transceivers Wizard