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AR# 55154

LogiCORE IP Serial RapidIO Gen2 Core v2.0 - Design might not meet timing for certain configurations of the core


Version Found: v2.0
Version Resolved and other Known Issues for v2.0 core: See (Xilinx Answer 54648)

For certain configurations of the LogiCORE IP Serial RapidIO Gen2 Core  v2.0 core, the design might not meet timing.


The users are advised to consult the section 'Clock Management' under the chapter 'Constraining the Core' of the LogiCORE IP Serial RapidIO Gen2 Core v2.0 core product guide for guidance on how to meet the timing.

Revision History:
04/03/2013 - Initial Release

AR# 55154
Date Created 03/26/2013
Last Updated 04/05/2013
Status Active
Type General Article
  • RapidIO