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  1. Xilinx - All Programmable
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  3. AR# 5516: 1.5i SP2 Bitgen -Bitstream for 4000X* and SpartanXL bitstream is incorrect for IFD with clock enable.

AR# 5516

1.5i SP2 Bitgen -Bitstream for 4000X* and SpartanXL bitstream is incorrect for IFD with clock enable.

Description

The bitstream for the xc4000XL(A) and SpartanXL IFD with a clock enable
is incorrect. The problem is that the IFD is clocking the new data in when
the enable is inactive. The problem seems to be that the clock enable
mux is using the feedback from the master latch instead of the slave latch.

Solution

A fix for this problem is available in the 1.5i Service Pack2:

(Xilinx Solution #5887)


AR# 5516
Date 04/19/2000
Status Archive
Type General Article