2. Support
  3. AR# 5516: 1.5i SP2 Bitgen -Bitstream for 4000X* and SpartanXL bitstream is incorrect for IFD with clock enable.
  4. AR# 55160: Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support

AR# 55160

Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support

Description

This Answer Record contains child Answer Records covering Synthesis attributes supported by Vivado Synthesis via HDL. 

These ARs provide coding examples for supported Synthesis HDL attributes. The AR also contains information related to known issues and good coding practices.

Note: This Answer Record is a part of the Xilinx Solution Center for Vivado Synthesis (Xilinx Answer 55265), which is available to address all questions related to Vivado Synthesis. 

Whether you are starting a new design or troubleshooting a problem, use the Solution Center for Vivado Synthesis to guide you to the right information.

Solution

The Attribute ARs contain the following child ARs covering the various Synthesis HDL attribute support.
 
(Xilinx Answer 54699) Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - dont_touch, full_case, gated_clock, shreg_extract.
(Xilinx Answer 53887) Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - black_box, io_buffer_type, clock_buffer_type, max_fanout.
(Xilinx Answer 54357) Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - parallel_case, translate_off/translate_on, use_dsp48
(Xilinx Answer 54778) Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - keep, keep_hierarchy, ram_style, rom_style
(Xilinx Answer 60799) Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - fsm_encoding, fsm_safe_state, srl_style

Note: Attribute success can be verified by the following methods:
 
  • Viewing the synthesized netlist using the "write_verilog", "write_vhdl" commands.
  • Opening the synthesized netlist design schematic viewer.
  • Using the "get_property" command on the TCL console as follows:

    get_property <PROPERTY_NAME> [get_<applicable_element> <element_instance_name>]>

    For example, get_property BLACK_BOX [get_cells my_inst]

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
55264 Xilinx Solution Center for Vivado Synthesis - Design Assistant N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
54699 Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - dont_touch, full_case, gated_clock, shreg_extract N/A N/A
53887 Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - black_box, io_buffer_type, clock_buffer_type, max_fanout N/A N/A
54357 Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - parallel_case, translate_off/translate_on, use_dsp48 N/A N/A
54778 Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - keep, keep_hierarchy, ram_style, rom_style N/A N/A
AR# 55160
Date 06/04/2014
Status Active
Type Solution Center
Tools