We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
AR# 55192: MIG 7 Series - Using the ChipScope tool in Vivado Design Suite
MIG 7 Series - Using the ChipScope tool in Vivado Design Suite
In the Vivado 2013.1 Design Suite, the ChipScope tool is being replaced with the Vivado Logic Analyzer. However, MIG does not yet support using Vivado Logic Analyzer, so users must continue using the ChipScope tool for debugging purposes.
The Vivado 2013.1 Design Suite still supports ChipScope cores, and the MIG example design with the debug signals enabled can be created and used by following these steps:
Create your Vivado project.
Locate MIG 7 Series from the IP Catalog.
Right-click MIG 7 Series and choose "Customize IP...".
Enable the Debug Signals for Memory Controller (ON), select the rest of the options, and click "Generate".
Right-click the MIG XCI file located in the sources window and choose "Generate Output Products...".
Generate select all output products that have not been generated and click OK.
Right-click the MIG XCI file located in the sources window and choose "Open IP Example Design".
Select Sub-direction location and click OK.
Once the Example Design is created and opened in a new Vivado project window, you are now ready to run through synthesis, implementation, and bitstream generation.
After bitstream generation the *.bit file can be used in ChipScope standalone.
Revision History 05/07/2013 - Updated to include debug option 04/03/2013 - Initial release