We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55194

Vivado Synthesis - What are Vivado Synthesis best practices for SystemVerilog?


This answer record explains Vivado Synthesis best practices for SystemVerilog.


The following are the Vivado Synthesis best practices for SystemVerilog:

  • Do not mix 2-state and 4-state types.
  • Unique and Priority are runtime checks.

        - As Unique and Priority are runtime checks they should be used cautiously in synthesis.

  • Use Always_ff/Always_latch/Always_comb.
  • Strings are supported as literals.

        - String is a dynamic type in SystemVerilog and hence not synthesizable.

  • Use fully specified modports for best results.
  • Use .* for modular code with minimum connection errors.
  • Functions are automatic by default.
  • To enable RAM extraction, read/write in same module.
  • Use enum instead of localparam.


AR# 55194
Date 04/03/2013
Status Active
Type Known Issues
Page Bookmarked