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AR# 55225

Vivado Synthesis - How can I avoid longer constraint validation times during early development cycles?

Description

How can I avoid longer constraint validation times during early development cycles?

Solution

The Vivado flow does constraint validation by default when synthesis is called. The constraint validation time can take longer during synthesis stage. Xilinx recommends that users not provide XDC constraints during early RTL development and cleanup stages. These can be included later when timing closure of implementation is being worked on.

Work is in progress to reduce the long constraint validation times permanently in future releases.

AR# 55225
Date Created 03/28/2013
Last Updated 06/19/2013
Status Active
Type Known Issues
Tools
  • Vivado Design Suite