AR# 55242


LogiCORE IP FIR Compiler v7.0 - Post-synthesis and post-implementation netlist output mismatches behavioral simulation output


If I simulate FIR Compiler v7.0 using Vivado Design Suite 2013.1, the post-synthesis and post-implementation netlist output mismatches the behavioral simulation output in the following ways:

  • Simulation of the post-synthesis netlist will give persistent mismatches on M_AXIS_DATA_TDATA when compared to the simulation model.
  • Simulation of the post-implementation netlist or operation in hardware will mismatch the desired behavior (i.e., the simulation model) for a short time (i.e., the data latency of the core) immediately following reset, but this is transient and will flush through.


This is a known issue with FIR Compiler v7.0. The error is confined in the following configurations of the core:

  • ARESETn = TRUE and
  • Data Vector Reset = TRUE and
  • Architecture = Fractional Decimation or any of the Transpose architectures.

The reason for the error is misconfiguration of the reset signal to the data block RAM in the core.

To work around this issue, do not use data reset with FIR Compiler v7.0 core.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54502 IP Release Notes and Known Issues for LogiCORE IP FIR Compiler core for Vivado 2013.1 and newer tools N/A N/A
AR# 55242
Date 08/22/2013
Status Active
Type General Article
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