If I simulate FIR Compiler v7.0 using Vivado Design Suite 2013.1, the post-synthesis and post-implementation netlist output mismatches the behavioral simulation output in the following ways:
This is a known issue with FIR Compiler v7.0. The error is confined in the following configurations of the core:
The reason for the error is misconfiguration of the reset signal to the data block RAM in the core.
To work around this issue, do not use data reset with FIR Compiler v7.0 core.