AR# 55249

Design Assistant for Vivado Synthesis - XDC Synthesis Attributes Support; MARK_DEBUG, KEEP_HIERARCHY, IOB, USE_DSP48

Description

This answer record shows the support of some of the Vivado synthesis properties in XDC:

MARK_DEBUG, KEEP_HIERARCHY, IOB, USE_DSP48

Example codes and constraints are attached to the end of this answer record.

Solution

MARK_DEBUG

This property tells the tool that certain nets will be used for debugging purpose.

Example:  set_property MARK_DEBUG TRUE [get_nets u/temp*]

This property is working in the current version of the tool but the report does not mention that the property is set.


KEEP_HIERARCHY

The property/attribute is used to prevent optimizations along the hierarchy boundaries. 

This can only be set in the RTL and not via XDC.


IOB

This property tells the tool that a register should be packed into IOB during implementation.

The application of this property on ports is now possible in the current version of Vivado 

Example set_property IOB TRUE [get_ports out*]

This property is working in the current version of the tool and can be set via XDC.


USE_DSP48

This property instructs the synthesis tool how to infer arithmetic structures, namely in the use of DSP48 primitives.

Example:  set_property use_dsp48 yes [get_nets sum*]

This property is supported in the current version of the tool and can be set via XDC.


Codes and Constraints examples:

Table 1-1

Coding example name Property
Mark_debug.xpr.zip
  • mark_debug
keep_hier.zip
  • keep_hierarchy
IOB.xpr.zip
  • IOB
dsp_style.xpr.zip
  • use_dsp48

Attachments

Associated Attachments

Name File Size File Type
keep_hier.zip 39 KB ZIP
MARK_DEBUG.xpr.zip 34 KB ZIP
IOB.xpr.zip 651 KB ZIP
dsp_style.xpr.zip 8 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
55260 Design Assistant for Vivado Synthesis - XDC Synthesis Attributes and Timing Constraints Support N/A N/A
AR# 55249
Date 06/04/2014
Status Active
Type Solution Center
Tools