This answer record describes how the Synthesis tool processes some XDC timing constraints:
Support for these properties
It is advised to have timing constraints in the XDC during Synthesis because the Synthesis tool, being timing-driven, uses these constraints as guides when doing optimization.
At the moment, the Synthesis report does NOT mention the timing constraints that are processed by the Synthesis tool.
As a result, you will have to open the synthesized netlist and query for them (for example, using report_timing) to confirm that the constraints were applied.
This XDC command is used to create a clock and It is the main timing constraint in any design.
Using the get_clock command with the opened Synthesized netlist will return the list of clocks and you can confirm if the clock was created during synthesis.
This XDC command is used to constrain the input paths.
Use report_timing to get a report of the path and to confirm if the input delay was applied correctly.
The input delay will be listed and the value can also be confirmed.
report_timing -from [get_ports datain2]
This XDC command is used to constrain the output paths.
Use report_timing to get a report of the path and confirm if the output delay was applied correctly.
The output delay will be listed and the value can also be confirmed.
report_timing -to [get_ports dataout]
This XDC command is used to disable timing paths.
Use report_timing to confirm that the slack is 'inf' to confirm that it was applied.
report_timing -from [get_cells data3_reg] -to [get_cells data4_reg]
This XDC command is used to set multicyle paths.
Use report_timing to confirm that the requirement is set to the requested multiplication factor.
report_timing -from [get_cells data2_reg] -to [get_cells data3_reg]
Example code for the Timing Constraints
The attached timing_constraints.zip file contains an example code that demonstrates processing timing constraints during synthesis.
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