How can I set the input and output delays to constrain the pure combinatorial pad to pad paths?
You can take advantage of virtual clocks, which
represent the clock at the external device connected to the FPGA, to
constrain this type of path.
A basic XDC constraint for this type of set-up is shown below:
For more information on constraining the input to output feed-through paths (pad to pad paths), please refer to UG949 - "UltraFast Design Methodology Guide for the Vivado Design Suite".