To drive consistency across Xilinx IP, mixed case signal names have been changed to use all lowercase for all VHDL and Verilog-based Xilinx cores.
If you are creating a new IP core in Vivado Design Suite 2013.1, this should have no affect.
However, if you have an existing design (created in Vivado 2012.4 or ISE 14.4 or earlier tools) which instantiates an IP core, an interface port name mismatch may appear if the IP core is upgraded in Vivado Design Suite 2013.1 or later tools to use the latest IP version.
If there is a port mismatch, instantiating the design module must be changed to match the latest port names.
The links below provide specific details for IP affected by this change.