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AR# 55309

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.5/v2.0 - ERROR:Place:1340 - PAD.pci_exp_rxn<1> is tied to GTHE_CHANNEL.pcie3_7x_v1_4_i/inst/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[1]

Description

Version Found: v1.5/v2.0
Version Resolved and other Known Issues: See (Xilinx Answer 47441) for v1.5, (Xilinx Answer 54648) for v2.0
 
When implementing the Virtex-7 FPGA Gen3 Integrated Block for PCI Express (v1.5 and v2.0) example design generated for 7vx980t-ffg1930-2 device in x8 configuration with PCIe location of X0Y0, the tools run into the following error message:
 
Running Implement.bat encountered  an error
ERROR:Place:1340 - PAD.pci_exp_rxn<1> is tied to
   GTHE_CHANNEL.pcie3_7x_v1_4_i/inst/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[1]
   .gt_wrapper_i/gth_channel.gthe2_channel_i which is locked to
   Site.GTHE2_CHANNEL_X1Y10
   This forces the PAD.pci_exp_rxn<1> to be locked to Site.IPAD_X2Y78 which is
   unbonded on the device!
 
This error is specific to the ffg1930 device package only.

Solution

This is a known issue and is scheduled to be fixed in a future release of the core. The X0Y0 PCIe block location is not valid for the ffg1930 device package. To resolve this issue, select X0Y1 in the core configuration GUI instead of X0Y0.
 
Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
 
Revision History:
04/03/2013 - Initial Release
AR# 55309
Date Created 04/02/2013
Last Updated 08/02/2013
Status Active
Type Known Issues
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)