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AR# 55311

7 Series Integrated Block for PCI Express v1.9/v2.0 - Downstream Memory Write transactions fail in VHDL example design simulation for the core generated with 128-bit interface width


Version Found: v1.9/v2.0

Version Resolved and other Known Issues:

When simulating a 7 Series Integrated Block for PCI Express v1.9/v2.0 VHDL example design generated for 128-bit interface width, downstream Memory Write transactions fail.


This is a known issue and is scheduled to be fixed in a future release of the core.

To work around this issue, make the following modification in PROC_TX_MEMORY_WRITE_64 in "test_interface.vhd":

 case ((int_length -1) mod 4) is
        --when 1 => trn_trem_n_c <= "11";
        --when 2 => trn_trem_n_c <= "10";
        --when 3 => trn_trem_n_c <= "01";
        --when 0 => trn_trem_n_c <= "00";
          when 0 => trn_trem_n_c <= "11";
          when 1 => trn_trem_n_c <= "10";
          when 2 => trn_trem_n_c <= "01";
          when 3 => trn_trem_n_c <= "00";
          when others => null;
      end case;

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

04/03/2013 - Initial release

AR# 55311
Date 09/14/2015
Status Active
Type General Article
  • 7 Series Integrated Block for PCI Express (PCIe)