The Write Context ID event (event 0x0B) of the Performance Monitoring Unit increments a counter only when an instruction that writes to the Context ID register, CONTEXTIDR, is executed. However, because of this issue, an instruction that reads the Context ID register also updates this counter.
Under the following conditions, the PMU updates the counter when it should not:
1. A PMU counter is enabled by setting the PMCNTENSET.Px bit to 1 (x identifies a single event counter, and takes a value from 0 to 7).
2. The Write Context ID event is mapped to this selected PMU counter:
a) The chosen PMU counter is selected, by setting PMSELR.SEL to x (the same value as in condition 1).
b) The Write Context ID event is mapped to this selected PMU by setting PMXEVTYPER.evtCount to 0x0B.
3. The PMU is enabled, by setting the PMCR.E bit to 1.
4. A read access occurs to the CONTEXTIDR.
Trivial. The erratum affects the accuracy of the Write Context ID event, and its associated PMUEVENT output signal.
Systems that use the CPU Performance Monitor Unit.
|Device Revision(s) Affected:||All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences Answer Record.|
|Third Party Errata:||ARM Errata 795769|