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AR# 55328

Zynq-7000 AP SoC, APU - DBGPRSR Sticky Reset status bit is set to 1 by the CPU debug reset instead of by the CPU non-debug reset

Description

The ARM architecture specifies that the processor sets the Sticky Reset Status Bit, DBGPRSR[SR], to 1 when the non-debug logic of the processor is in reset state. Instead, the processor sets this bit to 1 when the debug logic of the processor is in reset state.

Solution

This issue may cause two problems:

  DBGPRSR.SR might not be set to 1 when it should, when the non-debug logic of the processor is in reset state.
  DBGPRSR.SR might be set to 1 when it should not, when the debug logic of the processor is in reset state.

In both cases, the DBGPRSR.SR bit value might be corrupted which might prevent the debug logic from correctly detecting when the non-debug logic of the processor has been reset.

Impact:
Trivial.
Work-around:
None.
Configurations Affected:
Systems that use the CPUs.
Device Revision(s) Affected: All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences Answer Record.
Third Party Errata: ARM Errata 799770

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 55328
Date Created 04/02/2013
Last Updated 05/16/2013
Status Active
Type Design Advisory
Devices
  • XA Zynq-7000
  • Zynq-7000
  • Zynq-7000Q