This issue may cause two problems:
DBGPRSR.SR might not be set to 1 when it should, when the non-debug logic of the processor is in reset state.
DBGPRSR.SR might be set to 1 when it should not, when the debug logic of the processor is in reset state.
In both cases, the DBGPRSR.SR bit value might be corrupted which might prevent the debug logic from correctly detecting when the non-debug logic of the processor has been reset.
Systems that use the CPUs.
|Device Revision(s) Affected:||All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences Answer Record.|
|Third Party Errata:||ARM Errata 799770|