AR# 55351

AXI Bridge for PCI Express v1.06.a - Missing completion for Memory Read when configured as RC x4Gen2 on Zynq devices


Version Found: v1.06.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

When the AXI Bridge for PCI Express v1.06.a core is configured as x4Gen2 Root Complex for a Zynq device, the core does not send the corresponding CplD TLP in response to the read from the endpoint.


This is a known issue and will be fixed in the next release of the core.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
04/03/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 55351
Date 04/04/2013
Status Active
Type Known Issues