The XADC or SelectIO Example Design fails simulation in ISim with a fatal error similar to the below.
Why does this occur and is there any workaround?
This occurs due to a problem within the ISim name mapping of the "simtimeprint" procedures defined in the testbench.
There are multiple "simtimeprint" procedures in the testbench file, which conflict with the same name in the generated code.
To work around this issue, rename the procedures in VHDL, for example by adding a suffix 1, 2, and 3.
An example modified testbench is attached.
Vivado simulator does not error out for the design.
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