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AR# 55436

2013.1 IP Flows - Warning message ([Designutils 20-729]) issues when generating an IP core which contains a sub-core


When an IP core is generated that includes a sub-core, I get a warning such as:

[Designutils 20-729] "tri_mode_eth_mac_v5_5" not found in library "work"; using library "tri_mode_eth_mac_v5_5" instead for instantiation in architecture "tri_mode_ethernet_mac_v5_5_0_block".

Is this expected? Have I set up my project or IP repositories incorrectly?


This message is correct but is unneeded.  All IP cores written in VHDL should be compiled into their own library "corename_vX_y" as part of our IP standards, not into the work library.

This message will be suppressed in Vivado 2013.2.

AR# 55436
Date 06/17/2013
Status Archive
Type Known Issues
  • Vivado Design Suite - 2013.1
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