I have a Vivado design where I use a Synplify netlist and when I try to write a bitstream I receive the following drc error:
Why is this happening?
This error can occur when using the pre-packing feature of Synplify and then running Implementation with Vivado.
The lower 32 bits of these equations do not match. This is caused by the pre-packing feature.
This has been fixed in Vivado 2013.3 and we recommend updating to the latest software.
If this is not possible, you can work around thisby reloading the design.
This can be done in the GUI by selecting "Generate Bitstream" when an implementation run has completed.
Alternatively, this can be done in a batch flow by adding the following commands after route_design: