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  1. Xilinx - All Programmable
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  3. AR# 55529: 7 Series Integrated Block for PCI Express v1.9/v2.0 - CDC (Clock Domain Crossing) Issue

AR# 55529

7 Series Integrated Block for PCI Express v1.9/v2.0 - CDC (Clock Domain Crossing) Issue

Description

Version Found: v1.9/v2.0
Version Resolved and other Known Issues: See (Xilinx Answer 40469) for v1.9
                                                                   See (Xilinx Answer 54643) for v2.0

It has been found that some signals in the following files have a CDC issue:

pcie_7x_0_pipe_wrapper.v
pcie_7x_0_pipe_sync.v
pcie_7x_0_pipe_reset.v
pcie_7x_0_gtp_pipe_reset.v

Solution

This is a known issue that may show up in Clock Domain Crossing reports, but it will not manifest any issues in hardware due to how the impacted signals are used in the design.  An RTL fix will be available in the next release of the core. There is no functional implication on the core due to this issue and hence the issue can be ignored. However, it is recommended to update the core with the next release in 2013.2, which will have the updated wrapper with CDC fix and other enhancements.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


Revision History:

04/15/2013 - Initial release
06/11/2013 - Added information on 2013.2 release.

AR# 55529
Date 06/19/2013
Status Active
Type Known Issues
IP
  • 7 Series Integrated Block for PCI Express (PCIe)