AR# 5553: 1.5i Virtex Back Annotation - Simulation errors during physical back annotation (no .ngm) due to clock renaming by map.
AR# 5553
1.5i Virtex Back Annotation - Simulation errors during physical back annotation (no .ngm) due to clock renaming by map.
Description
The symptom is the mapper produces a GCLKIOB comp whose name ("clock") collides with its output signal name. When ngdanno tries to name the top level port/signal after the IOB comp, the name collision is detected and that signal name is changed from "clock" to "clock_p". This causes the simulation problem.
signal CLOCK : STD_LOGIC; ^ **Error: vhdlan,1072 rphy.vhd(108): Illegal redeclaration of CLOCK. I => CLOCK_P, ^ **Error: vhdlan,575 rphy.vhd(809): CLOCK_P is not declared.