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AR# 55536

Design Advisory for MIG 7 Series LPDDR2 - MIG allows incorrect placement of CK/CK# pairs when using the "Verify Pin Changes and Update Design" and "Fixed Pin-Out" flows

Description

Version Found: MIG 7 Series v1.9
Version Resolved: See (Xilinx Answer 54025)

The 7 Series FPGAs Memory Interface Solutions User Guide (UG586) properly states the following LPDDR2 design requirement:

  • CK must be connected to a DQSCC pair in one of the control byte groups.

When generating a MIG 7 Series LPDDR2 interface using the "New Design" flow, this design requirement is properly followed during pin-out generation. However, if a pin-out violating this requirement is uploaded to either "Verify Pin Changes and Update Design" or "Fixed Pin-Out" , the tool incorrectly allows CK/CK# pairs to be allocated to non-DQSCCIO pairs and generates a design.

Solution

All MIG 7 Series LPDDR2 designs generated using the "Verify Pin Change and Update Design" or "Fixed Pin-Out" flows MUST manually verify that the CK signals are placed on DQSCCIO pairs. The tool will properly include this DRC check and not allow designs with this pin-out violation to be generated starting with MIG 7 Series v2.0.

Revision History
04/15/13 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 55536
Date Created 04/12/2013
Last Updated 04/15/2013
Status Active
Type Design Advisory
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series