Version Found: MIG 7 Series v1.9
Version Resolved: See (Xilinx Answer 54025)
The 7 Series FPGAs Memory Interface Solutions User Guide (UG586) properly states the following LPDDR2 design requirement:
When generating a MIG 7 Series LPDDR2 interface using the "New Design" flow, this design requirement is properly followed during pin-out generation. However, if a pin-out violating this requirement is uploaded to either "Verify Pin Changes and Update Design" or "Fixed Pin-Out" , the tool incorrectly allows CK/CK# pairs to be allocated to non-DQSCCIO pairs and generates a design.
All MIG 7 Series LPDDR2 designs generated using the "Verify Pin Change and Update Design" or "Fixed Pin-Out" flows MUST manually verify that the CK signals are placed on DQSCCIO pairs. The tool will properly include this DRC check and not allow designs with this pin-out violation to be generated starting with MIG 7 Series v2.0.
04/15/13 - Initial release