AR# 55537


7 Series Integrated Block for PCI Express v1.9/v2.0 - How do you generate the core for production Zynq devices?


Version Found: v1.9/v2.0
Version Resolved and other Known Issues: See (Xilinx Answer 40469) for v1.9; (Xilinx Answer 54643) for v2.0

In Vivado 2013.1 and ISE 14.5 design tools, the core customization GUI allows you to select only 'Initial ES' and 'General ES' when generating the core for Zynq devices. How do I target production Zynq silicon?


For production Zynq silicon, please use the General ES (GES) option. The wrapper for both General ES and Production is the same. The GUI option will be fixed  in the next release of the core.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/02/2013 - Initial release

AR# 55537
Date 05/18/2018
Status Active
Type General Article
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