Data failures can occur when using the MIG 7 Series QDRII+ design with Fixed Latency mode enabled. This can occur when the read latency for one or more data byte lanes determined during calibration is longer than the specified Fixed Latency (PHY_LATENCY parameter) and the others are not.
Line 817 always @(posedge clk) begin Line 818 if (rst_clk) Line 819 cal_stage2_done <= #TCQ 0; else if (error_adj_latency) cal_stage2_done <= #TCQ 0; Line 820 else Line 821 cal_stage2_done <= #TCQ |lat_adj_done; Line 822 end
05/09/2013 - Added RTL fix
05/02/2013 - Initial release