UPGRADE YOUR BROWSER
We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
This answer record includes resolutions for two issues. The patch files attached at the end of this answer record include both required fixes.
Both issues are resolved in the Vivado 2013.2 Design Suite for non SSI parts.
For SSI parts, issue is resolved in Vivado Design Suite 2013.3.
It is not recommended to enable Readback CRC when the SEM IP is included in a design. The features include redundant functionality. SEM IP is not tested with Readback CRC enabled.
To work around this issue, a patch can be applied to your installation. Any design using Readback CRC or the SEM IP core should re-run Bitgen or write_bistream using a patched version of the tools.
Vivado Design Suite 2013.1
Following are installation instructions that can be applied across all platforms:
Vivado Design Suite 2012.4
Following are installation instructions that can be applied accross all platforms
ISE Design Suite 14.4
Following are installation instructions:
SSI device user: Vivado Design Suite 2013.2
User that use Readback CRC or SEM IP need to use 2013.3 tool. It is supported to only apply write_bitstream with 2013.3 of design that completed place and route in 2013.2.
Name | File Size | File Type |
---|---|---|
AR55673_14.4.zip | 35 MB | ZIP |
AR55673_2012.4.zip | 45 MB | ZIP |
AR55673_2.zip | 43 MB | ZIP |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
54642 | Soft Error Mitigation IP Core - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions | N/A | N/A |