We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55704

Zynq-7000 Example Design, EDK 14.5 - Generate and View AXI Cycles on HP Port


Attached is a simple XPS/SDK design with the AXI Exerciser core connected to an HP port. 

Control is provided through a GP port to the core.

The example code generates single and burst cycles to the HP port. 

The cycles can then be viewed using ChipScope Pro Analyzer.

It is a useful example to show AXI cycles taking place in the PL to the PS for customers designing their own AXI masters, or to get an idea on latencies based on different type of cycles.

Tools needed:

  • XPS 14.5
  • SDK 14.5/2013.1
  • ChipScope Pro 14.5

Hardware needed:

  • ZC702 board and cables

Hardware Design:

  • Processing System configured for the ZC702
  • AXI Exerciser connected to a HP port (configured for 64-bit) and GP port (control)
    • Due to a bug in the MPD file, a local pcore is provided with the project
  • AXI ChipScope Monitor
    • One core at the AXI4 master interface of the AXI Exerciser
    • One core at the AXI3 slave interface of the HP port

Software Application:

  • Simple standalone application to set up 4 transfers for the AXI Exerciser core
    • First transfer: Single cycle 64-bit write.
    • Second transfer: Single cycle 64-bit read. Transfer waits upon completion of first transfer.
    • Third transfer: 8 64-bit burst write. Transfer waits upon completion of second transfer.
    • Fourth transfer: 8 64-bit burst read. Transfer waits upon completion of third transfer.



  • Hardware:
    1. Open the XPS design
    2. Generate the bit file


  • Software
    1. Open SDK
    2. Import the existing SDK projects
    3. Recompile


  • Power-up the board
  • In SDK, download the bit file
  • Open ChipScope Pro Analyzer
    • Use the ChipScope Pro project file provided
  • Start a debug session in SDK for the application
  • ARM the triggers in CSPro
  • Hit continue in SDK
  • The Analyzer should trigger on the first AXI transaction




Associated Attachments

Name File Size File Type
ZC702_HP64_Exe_145.zip 1 MB ZIP
AR# 55704
Date 10/27/2017
Status Active
Type General Article
  • Zynq-7000
  • EDK - 14.5
  • AXI Exerciser
  • ChipScope AXI Monitor
Boards & Kits
  • Zynq-7000 SoC ZC702 Evaluation Kit
Page Bookmarked