We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55707

14.5 EDK, Zynq-7000 - FSBL unable to boot when using 32-bit HP AXI ports


When using the HP AXI ports at a 32-bit width in 7045ES and production Zynq devices, the FSBL is unable to boot and the CPU appears to be hung, with no access from JTAG. How do I resolve this issue?


In 7045ES and production Zynq devices, the bootROM no longer clears the required reserved bits in the FPGA_RST_REG register. When these reserved bits are '1', the HP/AFI registers cannot be accessed, causing a CPU hang. In the AXI HP 64-bit mode setting, the ps7_init function does not access the register.

This issue is planned to be fixed in the Xilinx FSBL starting in 14.6/2013.2.

To work around the issue, add the following code to the FSBL, above the function call of ps7_init():

Note: This workaround can be removed in version 14.6/2013.2 and later.

#define FPGA_RESET_MASK 0xf 
 Xil_Out32(FPGA_RESET_REG, FPGA_RESET_MASK); /*clear required 0 bits, leave FPGA resets active */
AR# 55707
Date 05/29/2013
Status Active
Type General Article
  • Zynq-7000
  • Zynq-7000Q
  • XA Zynq-7000
  • Vivado Design Suite - 2013.1
  • EDK - 14
  • EDK - 14.5
  • Processing System 7
Page Bookmarked