Constraints generated by FIFO Generator v10.0 in XDC file incorrectly sets the false path on output registers for synchronous Distributed RAM FIFO. This causes design failing in hardware
Here is the constraint mention in generated xdc file:
set wr_clock [get_clocks -of_objects [get_ports clk\]]
# Ignore paths from the write clock to the read data registers for Synchronous Distributed RAM based FIFO
set_false_path -from $wr_clock -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[*\]]
This is a known issue in the Vivado 2013.1 generated XDC file.
To resolve this issue, you must install the attached patch over your Vivado Design Suite 2013.1 installation.
To install the patch, unzip the contents of the ZIP file to the root directory of your Vivado tool installation. Installation instructions are available in the "readme" file that is attached.
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