AR# 55733

14.1 PlanAhead - Language option is not set for simulation and synthesis targets in the PlanAhead utility scripts when XPS project is imported


I import an XPS project into a PlanAhead project. The default language of XPS project is VHDL, and the default language of PlanAhead project is Verilog. When I refer to the directory XX/__xps/pa and check the XPS TCL API script generated by PlanAhead (the XX_sim.tcl and XX_synth.tcl), I find that the language option is not set.

The Tcl code for simulation and synthesis should contain the following command, such as:

    xset hdl verilog/VHDL


In ISE Design Suite 14.1, if a user is adding an existing XPS project to a PlanAhead project, they will need to make sure that the language settings match between the two. If the language on the XPS side needs to be changed, they can use XPS standalone tool to do that (or hand editing the .xmp file will work as well).

The issue is fixed in ISE Design Suite 14.2.

AR# 55733
Date 05/08/2013
Status Archive
Type Known Issues