In FPGA Editor, when I select the I0 and O pin of BUFG and click on the "delay" button in the user toolbar to report the BUFG component delay, it gives the following messages in the History toolbar:
The 1.076ns is obviously not the component delay of the BUFG. What is this delay?
What is the correct way to report a component delay?
The delay command (button) is to compute the delay for selected nets or paths.
For pins with multiple paths, the delay command computes the maximum delay path as the default.
The above messages indicate that there are multiple paths related to the selected pins and that the 5th path "SLICE_X0Y246.CLK" to "OLOGIC_X0Y245.D1" has the maximum delay which is 1.076ns.
A component delay is usually the minimum one in all the associated paths.
So to report the component delay, use the following method: