We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55761

FPGA Editor - How to report a component delay in FPGA Editor?


In FPGA Editor, when I select the I0 and O pin of BUFG and click on the "delay" button in the user toolbar to report the BUFG component delay, it gives the following messages in the History toolbar:

site.pin = BUFGCTRL_X0Y1.I0, comp.pin = clk1_BUFGP/BUFG.I0, delay = 2.413ns on net "clk1_BUFGP/IBUFG"
site.pin = BUFGCTRL_X0Y1.O, comp.pin = clk1_BUFGP/BUFG.O, delay = driver on net "clk1_BUFGP"
Path (5) "SLICE_X0Y246.CLK" to "OLOGIC_X0Y245.D1":

 1.076ns - Total, Path

The 1.076ns is obviously not the component delay of the BUFG. What is this delay? 

What is the correct way to report a component delay?


The delay command (button) is to compute the delay for selected nets or paths.

For pins with multiple paths, the delay command computes the maximum delay path as the default.

The above messages indicate that there are multiple paths related to the selected pins and that the 5th path "SLICE_X0Y246.CLK" to "OLOGIC_X0Y245.D1" has the maximum delay which is 1.076ns.

A component delay is usually the minimum one in all the associated paths. 

So to report the component delay, use the following method:

  1. Select the source and destination pins to be reported, for example, the I0 and O pins of the BUFG
  2. In the command line toolbar, run "delay -min" to report the minimum delay which is usually the component delay, or "delay -all" to list the delays of all associated paths. 
AR# 55761
Date 10/21/2014
Status Active
Type General Article
  • ISE Design Suite - 14