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AR# 55825

System Generator - FIFO, TO_/FROM_FIFO blocks do not simulate the latency correctly when "Use Embedded Register" is selected


If the Use Embedded Register option is enabled for the System Generator FIFO, TO_FIFO, FROM_FIFO blocks, the simulation shows incorrect latency (i.e., the latency through the core is there regardless of this option being enabled or not).

Why is this occurring?


This is a known issue in System Generator for the FIFO, TO_FIFO, and FROM_FIFO blocks. This is fixed in the ISE System Generator 14.6 and Vivado System Generator 2013.2 tools.

For now, it should be noted that this is a System Generator simulation issue only; the HDL netlist is correct and the System Generator project can be run in the ISE or Vivado simulators without issue.

It can also be seen that the DO_REG attribute is correctly set when this parameter is selected.

AR# 55825
Date 06/24/2013
Status Active
Type General Article
  • System Generator for DSP - 14.1
  • System Generator for DSP - 14.2
  • System Generator for DSP - 14.3
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  • System Generator for DSP - 14.4
  • System Generator for DSP - 14.5
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2012.4
  • Vivado Design Suite - 2012.3
  • Vivado Design Suite - 2012.2
  • Vivado Design Suite - 2012.1
  • System Generator for DSP - 14.6
  • Vivado Design Suite - 2013.2
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