I am trying to use timing constraints inside my VHDL or Verilog files.
However, I am not seeing any messages from Vivado tools about this constraint being accepted or rejected. I also do not see any indication from report_timing or report_timing_summary that indicates that my constraints were used.
Are in-line constraint okay for Vivado Synthesis?
Vivado tools do not support timing constraints embedded in RTL. Users should create a set_max_delay command and enter these constraints in an XDC file.
See UG903, Vivado Design Suite User Guide: Using Constraints, on the Xilinx website (www.xilinx.com) for constraint syntax and usage.