UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55859

PlanAhead - The wildcard pattern is not saved when I export constraints

Description

In the PlanAhead tool, I open the synthesized design and execute the following command in the TCL console:

Example from design "CPU (synthesized)")

%create_pblock pb1 
%add_cells_to_pblock pb1 [get_cells usbEngine0/u4/buf1*]
%write_xdc out.xdc
%save_design

For the new UCF syntax, I get the following:

INST "usbEngine0/u4/buf1_31" AREA_GROUP = "pb1";
INST "usbEngine0/u4/buf1_30" AREA_GROUP = "pb1";
INST "usbEngine0/u4/buf1_29" AREA_GROUP = "pb1";

However, I expected to get one line like the following:

INST "usbEngine0/u4/buf1*" AREA_GROUP = "pb1";

Why is my wildcard character not preserved?

Solution

The PlanAhead tool does not support wildcard operation for UCF.

In PlanAhead 14.1 and later, as well as in the Vivado tool, the wildcard pattern can be saved to cover pblock assignments in XDC.

Also, see (Xilinx Answer 47831).

Linked Answer Records

Associated Answer Records

AR# 55859
Date Created 05/03/2013
Last Updated 10/08/2013
Status Active
Type General Article
Tools
  • PlanAhead - 13