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AR# 55859

PlanAhead - The wildcard pattern is not saved when I export constraints


In the PlanAhead tool, I open the synthesized design and execute the following command in the TCL console:

Example from design "CPU (synthesized)")

%create_pblock pb1 
%add_cells_to_pblock pb1 [get_cells usbEngine0/u4/buf1*]
%write_xdc out.xdc

For the new UCF syntax, I get the following:

INST "usbEngine0/u4/buf1_31" AREA_GROUP = "pb1";
INST "usbEngine0/u4/buf1_30" AREA_GROUP = "pb1";
INST "usbEngine0/u4/buf1_29" AREA_GROUP = "pb1";

However, I expected to get one line like the following:

INST "usbEngine0/u4/buf1*" AREA_GROUP = "pb1";

Why is my wildcard character not preserved?


The PlanAhead tool does not support wildcard operation for UCF.

In PlanAhead 14.1 and later, as well as in the Vivado tool, the wildcard pattern can be saved to cover pblock assignments in XDC.

Also, see (Xilinx Answer 47831).

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AR# 55859
Date 10/08/2013
Status Archive
Type General Article
  • PlanAhead - 13
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